Packet optical communication networks typically involve a number of different clients with each client potentially using a different transmission rate for their data traffic. Thus, the network must accommodate the use of different rates by the multiple clients. To do so, the network uses multiple operating clocks to manage the data traffic. The multiple operating clocks are generated using dedicated analog phase locked loop (PLL) circuits in a semiconductor integrated circuit (chip) separate from the memory and logic chips used in the network devices for managing the data traffic and the device itself. However, the use of a separate clock chip increases the cost of the network device.
The network devices also include field-replaceable units (FRU), such as the separate clock chip. The FRU is a circuit board, part or assembly that can be quickly and easily removed from the network device and replaced by the user or a technician without having to send the entire device to a repair facility. FRUs allow a technician lacking in-depth product knowledge to isolate faults and replace faulty components. Unfortunately, the use of clocks that are PLLs on a FRU increases the amount of space required on the printed circuit boards of the network device. The use of a separate clock chip, therefore, presents a scaling issue with respect to FRU real estate on high rate devices (e.g. terabit rate clock FRUs).
Accordingly, there is a need for systems, apparatus, and methods that solves this problem by managing the rates of these multiple clients in the digital domain and thereby restricting the need for separate clock chips such as analog PLLs while allowing the network device to handle multiple clients with different data rates on the main chip including the improved methods, system and apparatus provided hereby.